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TE CH
T2316405A Preliminary T2316407A
DRAM
FEATURES
* Industry-standard x 4 pinouts and timing functions * power supply : T2316405A 2.6V(0.2V) T2316407A 3.3V(0.3V) * All device pins are TTL- compatible. * 2048-cycle refresh in 32 ms. * Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN. * Extended data-out (EDO) PAGE MODE access cycle.
4M x 4 DYNAMIC RAM
EDO PAGE MODE GRNERAL DESCRIPTION
The T2316405A and T2316407A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x 4 configuration. It offers Fast Page mode with Extended Data Output (EDO). During READ or WRITE cycles, each of the 4 memory bits (1 bit per I/O) is uniquely addressed through the 22 address bits, which are entered 11 bits (A0-A10) at a time. RAS latches the first 11 bits and CAS latches the latter 11 bits. A READ or WRITE cycle is selected w ith the WE input. A logic HIGH on WE dictates READ mode while a logic LOW on WE dictates WRITE mode. During a WRITE cycle, data -in is latched by the falling edge of WE or CAS , whichever occurs last. When WE goes Low prior to CAS going LOW ( EARLY WRITE cycle), the J S output pins remain open (High-Z) until the next CAS cycle. A Late Write or Read-Modify-Write occurs. When WE falls after CAS was taken LOW (Late Write cycle). OE must be taken HIGH to disable the data-outputs prior to applying input data. The four data inputs and four data outputs are routed through four pins using common I/O, and pin direction is controlled by WE and OE .
OPTION
TIMING 50ns (For T2316407A only) 60ns (For T2316407A only) 70ns (For T2316407A only) 100ns (For T2316405A only) PACKAGE 26/24-pin SOJ 26/24-pin TSOP-II MARKING -50 -60 -70 -10
PIN ARRANGEMENT (Top View)
Vcc I/O1 I/O2 WE RAS NC A10 A0 A1 A2 A3 Vcc 1 2 3 4 5 6 8 9 10 11 12 13 SOJ & TSOP-II 26 25 24 23 22 21 19 18 17 16 15 14 Vss I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 Vss
Taiwan Memory Technology, Inc. reserves the right P. 1 to change products or specifications without notice.
Publication Date: APR 2001 Revision:0.B
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WE CAS
TE CH
T2316405A Preliminary T2316407A
BLOCK DIAGRAM
4
DATA-IN BUFFER CONTROL LOGIC NO.2 CLOCK GENERATOR DATA-OUT BUFFER
IO1 IO2 IO3
4 4
IO4
OE COLUMNADDRESS BUFFER(11) 1
REFRESH CONTROLLER
11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11
10
COLUMN DECODER
1024
4
SENSE AMPLIFIERS I/O GATING
REFRESH COUNTER 11 COMPLEMENT SELECT ROW SELECT (2 of 4096) ROW DECODER ROWADDRESS BUFFERS (11) 2048 2048 2048 2048
1024
ROW TRANSFER (1 of 2)
11
2048
4096 x 1024 x 4 MEMORY ARRAY
RAS
NO.1 CLOCK GENERATOR Vcc Vss
PIN DESCRIPTION
PIN NO. 8~12,15~19,21 5 23 4 22 2,3,24,25 1,13 14,26 6 SYM. A0-A10 RAS
CAS
TYPE Input Input Input Input Input Input/ Output Supply Ground
DESCRIPTION Address Input Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input/ Output Power Ground No Connect
WE OE I/O1 -I/O4 Vcc Vss NC
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Publication Date: APR 2001 Revision:0.B
(1 of 2)
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Parameter
TE CH
T2316405A Preliminary T2316407A
ABSOLUTE MAXIMUM RATINGS
Symbol VT Vcc Iout PT TOPR Tstg Value -0.5 to 4.6 -0.5 to 4.6 50 1 0 to 70 -55 to 125 Unit V V mA W C C Voltage on Any Pin Relative To Vss Supply Voltage Relative To Vss Short circuit Output Current Power Dissipation Operating Temperature Storage Temperature
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to +70C ) For T2316405A-10 only
Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol Vss Vcc VIH VIL Min. 0 2.4 2.0 -0.3 Typ 0 2.6 Max. 0 2.8 Vcc+0.3V 0.8 Unit V V V V 1 1 1 Notes
(Ta = 0 to +70C ) For T2316407A-50/60/70 only
Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol Vss Vcc VIH VIL Min. 0 3.0 2.0 -0.3 Typ 0 3.3 Max. 0 3.6 Vcc+0.3V 0.8 Unit V V V V 1 1 1 Notes
Notes : 1. All voltages referenced to Vss
Taiwan Memory Technology, Inc. reserves the right P. 3 to change products or specifications without notice.
Publication Date: APR 2001 Revision:0.B
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TE CH
T2316405A Preliminary T2316407A
DC CHARACTERISTICS
(Ta = 0 to 70 C ) T2316405A-10 Vcc = 2.6V 0.2V, Vss = 0V T2316407A-50/60/70 Vcc = 3.3V 0.3V, Vss = 0V
Parameter -50 -60 -70 -10 Symbol Min Ma Min Ma Min Ma Min Ma Unit x x x x ILI ILO VOH VOL Icc1 -5 -5 2.0 5 5 0.8 95 -5 -5 2.0 5 5 0.8 90 -5 -5 2.0 5 5 0.8 80 -5 -5 2.0 5 5 0.8 50 uA uA V V mA Test Condition 0V Vin Vcc+ 0.3V Other pins = 0V 0V Vout Vcc Dout = disable High Iout= -2.0mA Low Iout=2.0mA
RAS , CAS cycling tRC =min TTL interface,
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Current
Standby Current
Icc2
-
2
-
2
-
2
-
2
mA RAS , CAS =VIH, DOUT=High-Z CMOS interface, RAS , CAS > Vcc-0.2V
Standby Current EDO Page Mode Current RAS -only refresh Current CAS Before RAS Refresh Current
Icc3 Icc4 Icc5 Icc6
-
0.5 95 95 95
-
0.5 90 90 90
-
0.5 80 80 80
-
0.5 mA 50 50 50 mA
RAS =VIL, CAS cycling, tPC = min CAS =VIH, RAS mA cycling, tRC = min mA
RAS ,CAS cycling,
tRC = min
Note:
Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition, Icc is specified as an average current.
CAPACITANCE
(Ta =25 C, f = 1M HZ, T2316405A-10 Vcc = 2.6V, T2316407A-50/60/70 Vcc = 3.3V)
Parameter Input Capacitance (address) Input Capacitance ( RAS , CAS , WE , OE ) Output Capacitance (data-in/out) C I2 C I/O 7 7 pF pF Symbol C I1 Typ Max 5 Unit pF
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Publication Date: APR. 2001 Revision:0.B
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TE CH
T2316405A Preliminary T2316407A
AC CHARACTERISTICS (note 1,2,3) (Ta = 0 to 70 C)
TEST CONDITIONS: T2316405A-10 Vcc = 2.6V 0.2V , T2316407A-50/60/70 Vcc = 3.3V 0.3V VIH/VIL =2.0/0.8V,VOH/VOL=2.0/0.8V Input rise and fall times: 2ns , Output Load: 2TTL gate + CL (100pF)
AC CHARACTERISTICS PARAMETER Read or Write Cycle Time Read Write Cycle Time EDO-Page-Mode Read or Write Cycle Time EDO-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From CAS Precharge RAS Pulse Width RAS Pulse Width (EDO Page Mode) RAS Hold Time RAS Precharge Time
CAS Pulse Width
SYM
-50
-60
-70 124 160 30 78 70
-10 180 240 40 120 100
UNIT Notes
Min Max Min Max Min Max Min Max
tRC 84 104 tRWC 108 135 tPC 20 25 tPCM 56 68 tRAC 50 60 tCAC 13 15 tOAC 13 15 tAA 25 30 tACP 30 35 tRAS 50 10K 60 10K tRASC 100 100 50 60 K K tRSH 8 10 tRP 30 40 tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR tRAL tRCS tRCH tRRH tCLZ tOFF1 38 10 12 5 0 8 10 0 8 21 25 0 0 0 0 0 12 37 40 10 14 5 0 10 12 0 10 24 30 0 0 0 0 0 15 45
20 25 20 25 35 50 40 55 70 10K 100 10K 100 100 70 100 K K 13 25
ns ns ns ns ns 4 ns 5 ns 13 ns 8 ns ns ns ns ns ns ns ns ns 7 ns ns ns ns 8 ns ns ns ns ns 14 9,14 ns ns ns 9
50 70 8 10K 10 10K 13 10K 25 10K 45 10 14 5 0 10 12 0 13 27 35 0 0 0 0 0 20 50 100 10 25 5 0 15 20 0 20 45 50 0 0 0 0 0 25 75
CAS Hold Time CAS Precharge Time (EDO Page Mode) RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time RAS to Column Address Delay Time Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time Read Command Setup Time Read Command Hold Time Reference to
CAS
25
30
35
50
Read Command Hold Time Reference to RAS
CAS to Output in Low-Z
Output Buffer Turn-off Delay From CAS or
RAS
ns
10,16
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Publication Date: APR. 2001 Revision:0.B
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TE CH
T2316405A Preliminary T2316407A
-50 -60 -70 -10 SYM Min Max Min Max Min Max Min Max tOFF2 tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR 0 0 8 21 8 10 8 0 8 21 12 0 0 10 24 10 10 10 0 10 24 79 49 34 50 2 5 10 10 10 5 5 10 7 5 10 15 50 32 5 10 10 13 5 5 10 10 5 20 15 0 0 13 27 10 13 13 0 13 27 94 59 44 2 50 32 5 10 10 25 5 5 10 13 5 25 20 0 0 15 40 15 25 25 0 20 45 130 80 55 2 50 32 25
AC CHARACTERISTICS (continued)
AC CHARACTERISTICS PARAMETER Output Buffer Turn-off to OE Write Command Setup Time Write Command Hold Time Write Command Hold Time (Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS )
RAS to WE Delay Time
UNIT Notes
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns
16 11,14
14 14 14 14 12 12
tRWD 64 tAWD 39 tCWD 26 tT tREF tRPC tCSR tCHR tOEH tOES tOEH C tOEP tORD 2 32 5 5 8 8 5 5 10 5 5
11 11 11 2,3
Column Address to WE Delay Time CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (2048 cycles)
RAS to CAS Precharge Time
CAS Setup Time (CBR REFRESH) CAS Hold Time (CBR REFRESH) OE Hold Time From WE During ReadModify-Write Cycle OE Low to CAS High Setup Time
OE High Hold Time From CAS High
6 6 15
OE High Pulse Width
OE Setup Prior to RAS During Hidden Refresh Cycle Data Output Hold After CAS Returning Low tCOH
Output Disable Delay From WE
tWHZ
Taiwan Memory Technology, Inc. reserves the right P. 6 to change products or specifications without notice.
Publication Date: APR. 2001 Revision:0.B
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TE CH
T2316405A Preliminary T2316407A
11. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY -WRITE cycles only. If t CS tWCS(min), the cycle is an W EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min), tAWD tAWD (min) and tCWD tCWD(min), the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE controlled) cycle. 12. These parameters are referenced to CAS leading edge in EARLY W RITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. 14. WRITE command is defined as WE going low. 15. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 16. The I/Os open during READ cycles once tOFF1 or tOFF2 occur.
Notes: 1. An initial pause of 200us is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake -ups should be repeated any time the tREF refresh requirement is exceeded. 2. V IH(2.0V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between V IH(2.0V) and VIL(0.8V). 3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. 4. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that t RCD exceeds the value shown. 5. Assume that tRCD tRCD(max) . 6. Enables on-chip refresh and address counters. 7. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, access time is controlled by tCAC. 8. Operation within the tRAD limit ensures that tRAC(max) can be met. tRAD(max) is specified as a reference point only; if tRAD is greater than the specified t AD(max) limit, R access time is controlled by tAA. 9. Either tRCH or tRRH must be satisfied for a READ cycle. 10. tOFF1 (max) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL .
Taiwan Memory Technology, Inc. reserves the right P. 7 to change products or specifications without notice.
Publication Date: APR. 2001 Revision:0.B
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TE CH
READ CYCLE
tR C tRAS
T2316405A Preliminary T2316407A
tRP
RA S V IH V IL
t C SH t R SH tC R P tR C D tCAS tRRH
CA S
V IH V IL tR A D tA S R tRAH RO W
tA R t R AL tA S C tCAH ROW t RC H
A DDR
V IH V IL
CO LUMN tR C S
WE V IH V IL
tA A t R AC t C AC tCLZ
N OTE 1 tO F F 1
V I/O V OH OL V IH V IL
OP EN tO A C
V A L ID D A T A tO F F 2
O PE N
OE
EARLY WRITE CYCLE
tR C tR A S RAS V IH V IL tR P
tC R P V C AS V IH IL tR A D tR A H ROW
t RC D
tC S H tR S H
tCAS
tA R tA S R tA S C tRAL tCAH ROW
A DDR
V IH V IL
CO LUMN tC W L tR W L t WC S tW C R tW P tW C H
WE
V IH V IL t DS
tD H R tD H V A L ID D A T A
V I/O V IOH IOL OE V IH V IL
DON'T CARE UNDEFINED
Note: tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
2Taiwan Memory Technology, Inc. reserves the right P. 8
to change products or specifications without notice.
Publication Date: APR. 2001 Revision:0.B
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TE CH
T2316405A Preliminary T2316407A
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t R WC tR A S tR P
RA S V IH V IL
tC R P V CA S IH V IL
t RC D
tC S H tR S H tC A S
tA R tR AD tA S R tR A H RO W tA S C tR AL tC A H RO W t R WD t C WD t A WD t C WL t R WL t WP
ADDR V IH V IL
COLUMN tR C S
WE
V IH V IL
tA A tR A C tC AC tC L Z tD S
V A LID D
t DH OPE N
I/O
V IOH V IOL V IH V IL
OP EN tO A C
OU T
V A L ID D
IN
tO F F 2
tO E H
OE
EDO-PAGE-MODE READ CYCLE
t RA S C tR P
RAS VIH V IL
tC R P
tC S H tR C D tC A S
tP C tC P tC A S tC P
tR SH t C AS
tC P N
V CA S VIH IL
t RA D t RA H
tA R tR A L tA S C t CA H tA S C t CA H tA S C t CA H tA S R
ADDR
VIH V IL
ROW tR C S
C O L U MN
C OLUMN
C OLUMN tR C H
ROW tR RH
WE VIH V IL
tA A tR A C tC A C tC L Z tC O H V A L ID D AT A tO A C tOES
t AA tA C P t CA C tC L Z V A LID DA T A tOFF2
tA A tA C P t CA C N OTE1 tO F F 1 V A L ID DA TA tO F F 2 OP EN
I/O
V OH V OL
O PE N
tO E H C
tO A C tOES
V OE VIH IL
tO E P
DON'T CARE UNDEF INED
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of CAS . Both measurements must meet the t PC specification.
2Taiwan Memory Technology, Inc. reserves the right P. 9
to change products or specifications without notice.
Publication Date: APR. 2001 Revision:0.B
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TE CH
T2316405A Preliminary T2316407A
EDO-PAGE-MODE EARLY-WRITE CYCLE
t R AS C
V RAS V IH IL
tC R P
tC S H tR C D t CA S
tP C tC P tC A S tC P
tR S H tC A S
tC P N
VIH CA S V IL
tA R tR A D tA S R tR A H tA S C t CA H tA S C tC A H tA S C tR A L tC A H
ADDR
V IH V IL
RO W
C O LU M N tW C S t CWL t WCH tWP
C O L U MN t WCS t CWL t WCH tWP
C O L U MN tW C S tC W L tW C H tW P
RO W
V WE V IH IL
tW C R tD H R t DS tD H tD S tD H tD S t RW L tD H
I/O
VIOH V IOL VIH V IL
V A L ID D A T A
V A L ID D A T A
VA LID DA TA
OE
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t R A SC tR P
V RAS V IH IL
t CR P t RC D
tC S H tC A S tC P
tPC M t CA S
tC P
tR S H tC A S
tC P N
CAS V IH V IL
tA R tR A D t AS R tR A H tA S C tC A H tA S C t CA H tA S C
t R AL tC A H
ADDR V IH V IL
RO W
C OLUMN tRW D tRC S tC W L tW P tA W D tC W D
C OLUMN
C OLUMN
RO W tR W L
tC WL tWP t AWD t CW D
tC W L tA W D tC W D tW P
WE
V IH V IL
t R AC
t AA tD H tC A C tC L Z tD S
tA A tA C P tC A C tC L Z
VALI D DO UT VAL ID DI N V ALI D D OUT VALI D DI N
tA A t DH t DS tA C P tC A C tC L Z
VALI D D OUT V ALI D DI N
tD S
tD H
I/O
V IOH V IOL
OP EN
OP EN
tO F F 2 tO A C tO A C
tO F F 2 tO A C
tO F F 2 tO E H
OE
V IH V IL
D ON 'T CAR E UNDEF INED
Note: tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tP C specification.
2Taiwan Memory Technology, Inc. reserves the right P. 10
to change products or specifications without notice.
Publication Date: APR. 2001 Revision:0.B
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V RAS V IH IL
TE CH
T2316405A Preliminary T2316407A
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
tR A S C tRP
tC S H t PC tCRP tR C D tCAS tCP tC A S t PC tC P tR S H tC A S tCP
V CA S V IH IL tR A D
tA R tA S R t R A H t AS C tC A H tA S C tC A H t AS C
tR A L tC A H ROW
V ADDR IH V IL
ROW
C O L U M N (A) tR C S
C OLU M N(B ) tR C H
C O L U M N (N ) tW C S t WC H
V IH WE V IL t R AC
tA A tCAC
tA C P
tA A tC A C tC O H
t WH Z
tD S
tD H
V IO H I/O V IOL
O PE N t OA C
V A L ID D A T A ( A )
V A L ID DA T A (B )
VALID DATA IN
V OE V IH IL
RAS ONLY REFRESH CYCLE (ADDR=A0-A10;O E , W E =DON`T CARE)
t RC tR A S RAS V IH V IL tR P
tCRP
tR P C
V CA S V IH IL
tASR ROW
tR A H RO W
V ADDR V IH IL V OH V OL
I/O
OP EN
DON'T CARE UNDEFINED
2Taiwan Memory Technology, Inc. reserves the right P. 11
to change products or specifications without notice.
Publication Date: APR. 2001 Revision:0.B
tm
RAS
TE CH
T2316405A Preliminary T2316407A
CBR REFRESH CYCLE (A0-A10; OE =DON`T CARE )
tRP tR A S tR P tR A S
VI H V IL
tRP C tC P N tC S R t CH R tRP C tC S R t CH R
CAS
VI H V IL
O PEN
I/O VI H V IL
tW RP
tW R H
tW RP
tW R H
WE
HIDDEN REFRESH CYCLE ( WE =HIGH;OE =LOW)
(R E A D ) tRA S tR P (R E F R E S H ) tRA S
RAS
V IH V IL V IH V IL
tC RP
tR C D
t RS H
tC H R
CAS
tA R t RAD tA S R tR A H tA S C tR A L tC A H
A D D R V IH V IL
ROW
C OL U MN tA A tR A C tC A C tC L Z N OTE1 tO FF 1
I /O
V OH V OL
OPEN t OAC
V A L ID D A T A tO F F 2
OPEN
OE
V IH V IL
tO RD
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
Taiwan Memory Technology, Inc. reserves the right P. 12 to change products or specifications without notice.
Publication Date: APR. 2001 Revision:0.B
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TE CH
T2316405A Preliminary T2316407A
PACKAGE DIMENSIONS 24-LEAD SOJ DRAM (300 mil)
SYMBOL A B C D E F G H I J K L M N O P Q y
DIMENSIONS IN INCHES 0.673 0.002 0.300 0.002 0.060 0.002 0.050 0.001 0.063 0.001 0.015 0.002 0.036 0.002 0.050 0.002 0.018 0.002 0.028 0.002 0.336 0.003 0.010 0.001 0.029 0.002 0.268 0.003 0.300 0.002 0.042 0.001 0.129 0.004 0.004(MAX)
DIMENTIONS IN MM 17.09 0.05 7.620.13 1.520.05 1.270.03 1.630.03 0.380.05 0.910.05 1.270.05 0.460.05 0.710.05 8.530.08 0.250.03 0.740.05 6.810.08 7.620.05 1.070.03 3.280.10 0.102(MAX)
Taiwan Memory Technology, Inc. reserves the right P. 13 to change products or specifications without notice.
Publication Date: APR. 2001 Revision:0.B
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TE CH
T2316405A Preliminary T2316407A
PACKAGE DIMENSIONS 24-LEAD TSOP II DRAM (300 mil)
"A"
SYMBOL A A1 A2 b D E E1 e L' L1' y
DIMENSIONS IN INCHES 0.047(MAX) 0.004 0.002 0.039 0.002 0.016 0.004 0.675 0.005 0.368 0.003 0.300 0.005 0.050 0.020 0.004 0.031 0.002 0.002 1~ 5
DIMENTIONS IN MM 1.20(MAX) 0.100.05 1.000.05 0.410.11 17.14 0.13 9.220.20 7.620.13 1.27 0.500.10 0.80 0.050.05 1~ 5
Taiwan Memory Technology, Inc. reserves the right P. 14 to change products or specifications without notice.
Publication Date: APR. 2001 Revision:0.B

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